In the Moore era of integrated circuits, active array antenna technology is a high-tech product integrating modern phased array antenna theory, semiconductor technology and optoelectronic technology. Amplifying components, etc. Active array antennas have thousands of T/R components, each T/R component is composed of an amplifier in the transmit chain, a low-noise amplifier in the receive chain, and a phase shifter, etc. . With the development of semiconductor technology, monolithic microwave integrated circuit (MMIC) technology, radio frequency microelectromechanical systems (RF MEMS) technology and integrated packaging technology are high performance, high reliability, The realization of miniaturized and low-cost T/R components provides a technological approach. In particular, integrated circuit technology is moving from narrow-band single-function to broadband multi-function, from monolithic integrated circuit (MIC) to system on chip (system on chip). , SoC), and from the multi-chip module (MCM) to the multi-function system in package (system in package, SiP) direction, the structure of T/R components is developed from brick to tile These have greatly promoted the development of active array antenna technology.The development of active array antenna technology continuously promotes the miniaturization, integration and low power consumption of communication, radar, and personal consumer electronics systems. The traditional active array antenna is a brick structure, which is composed of no source antenna array, a variety of functional modules and passive antennas are integrated together. For the miniaturization, multi-function, high performance, low power consumption, low cost and other requirements of the new generation of information systems, and with the development of semiconductor technology and With the development and drive of advanced packaging technology, new antennas such as antenna on chip (AoC), antenna in package (AiP), and system-in-package (SiP) have appeared. AoC and AiP belong to the concepts of SoC and SiP, respectively. Category. In addition to these types of antennas, there are also tiled antennas. The relationship between them is shown in Figure 1.AiP integrates the antenna in the package that carries the chip through packaging materials and processes. The packaging antenna technology inherits and develops the integration concept of microstrip antenna, multi-chip circuit module and tiled phased array antenna structure, extending the antenna antenna Compared with AoC, AiP integrates a variety of devices and circuits in one package to complete complex functions and specific system-level packaging that are difficult to achieve with on-chip antennas, effectively avoiding semiconductor substrates. The problem of gain loss caused by the low resistivity of the antenna, the radiation efficiency of the antenna generally reaches more than 80%. The package forms include direct chip attach (DCA), land grid array (LGA), four-side no Lead flat package (quad flat no lead, QFN), embedded wafer level ball grid array (embedded wafer level ball grid array, eWLB) package, and based on low temperature co-fired ceramics (low temperature co-fired ceramics, LTCC) package. The antenna array realized by thick film technology and the RF chip are packaged into a QFN package by gold wire bonding, and a packaged antenna with a center frequency of 122 GHz, a bandwidth of 12 GHz, and a maximum gain of 11.5 dBi is realized. A sample source array packaged antenna with a center frequency of 10 GHz, a bandwidth of 4 GHz, and a single-channel pulse power of 5 W.SiP adopts silicon-on-insulator (SOI) process and QFN packaging technology to combine on-chip antennas and packaged antennas to achieve a maximum antenna gain of 8 dBi in the frequency range of 54.5∼63.4 GHz . The dipole antenna is realized by the redistribution layer inside the eWLB package, and a dielectric lens is designed outside the package to improve the antenna gain. The antenna gain is 5.9 dBi when the lens is not installed, and the lens is installed. , the gain is boosted to 13.7 dBi.The structural feature of the tile-type array antenna is that the multi-functional circuit board also acts as the main body of the encapsulation shell, and it often does not use or rarely uses high-frequency and low-frequency connectors. The use of tile-type arrays can greatly reduce the thickness of the antenna system, extremely Significantly reduces the number of connectors and cables used. Commercial microwave packaging and fabrication techniques can be selected for RF modules, further reducing costs. This tiled array architecture uses an industry-standard QFN package with active circuit layers soldered directly on an inexpensive printed circuit board. On the printed circuit board (PCB), and then directly soldered to the back of the tile antenna array. The tile array antenna is shown in Figure 3.Figure 5 shows the comparison of two configurations of conventional active phased array antenna and antenna array integrated system. Figure 5(a) is a brick structure of active phased array antenna operating at 9.6 GHz, and the antenna thickness is 155 mm . Figure 5(b) and (c) are the radiation surface and the back of the integrated system of the antenna array, operating at 35 GHz, in the form of a tile structure, and the thickness of the antenna is 5 mm. If the research is carried out according to the concept of the antenna array microsystem, Integration and performance parameters can be further improved.In 1998, the Microsystems Technology Office (MTO) of the Defense Advanced Research Projects Agency (DARPA) proposed the concept of microsystems from a new perspective. Microsystems are the fusion of architecture, algorithms, microelectronics, microphotonics, MEMS and other elements, using new design ideas, design methods and manufacturing methods, integrate functions such as sensing, processing, execution, communication, energy, etc., microdevices with multiple functions. The DARPA microsystem concept goes beyond MEMS The understanding of microsystems (MEMS) provides space for multidisciplinary integration of microsystems, micro-scale integration, military application innovation, and miniaturization and performance improvement of electronic information systems, and promotes the advancement of microsystem integration methods and technologies. In 2017, DARPA Microsystems The System Office launched the Electronic Revival Initiative (ERI), and laid out six development projects in the three pillar areas of materials and integration, circuit design and system architecture.Microwave integrated circuits refer to integrated circuits that use advanced semiconductor technology to process microwave/analog signals by means of amplification, transformation, calibration, comparison and transmission. With the development of microwave integrated circuits and digital technology, the integration of microwave chips has become more and more High, the integrated circuit integrates multiple single-function chips on one chip, which improves the performance of the chip and reduces the cost. The microwave single chip can integrate the small-signal receiving chain and part of the transmitting chain circuit, and the receiving chain includes low noise amplifier, Frequency mixing, gain control, etc., and even high-performance analog-to-digital converters (ADCs), etc., and the transmission chain includes signal generation, frequency mixing, power amplifiers, etc. Different semiconductor materials have different properties. The characteristic parameters of several semiconductor materials are shown in Table 3. Si is usually used as the base material for digital/analog control or low-band power chips, and GaAs is often used as the base material for microwave radio frequency chips below the Ka band. SiC , GaN and diamond (diamond) are third-generation semiconductor materials that can have wide band gap (WBG) characteristics.Guided by the requirements of the antenna array microsystem architecture, based on the requirements of software definability and hardware reconfiguration, carry out research and design of multi-functional chips such as SOC based on IP module and application specific integrated circuits (ASIC), making breakthroughs IP core multiplexing technology, low-power design technology, testability technology, etc. At the same time, according to the characteristics of multi-physics coupling and multi-function integration in the micro-scale of the antenna array micro-system, the research on the adaptive software algorithm is carried out, focusing on solving the antenna array The problem of co-design of software and hardware in microsystems. Carry out chip design research around the function enhancement and heterogeneous process adaptation of antenna array microsystems, optimize control strategies, realize intelligent digital control, reduce system power consumption, and break through massive data real-time processing, ultra-high The technical bottleneck of high-frequency, ultra-high-speed and ultra-large-capacity data communication, as well as efficient thermal energy transfer, and improve internal auxiliary functions and protection functions, realize interface standardization, and improve the overall applicability and compatibility of antenna array microsystem hardware and software.A representative stack-type 3D package can be a stack of bare chips, and a stack of MCMs can even be a stack of wafers. The typical structure of 3D advanced packaging is shown in Figure 9. 3D-MCM can combine different process types Chips (such as analog, digital, and RF functional chips) realize the integration of mixed signals in a single package structure, meeting the mechanical performance requirements of antenna array microsystem modules, and in the case of extremely limited module size, weight and power consumption , By optimizing the thickness of the multi-functional circuit board, the thickness of the antenna array microsystem package can be reduced, and the integration density can be further improved. The core of 3D silicon chip integration is through silicon via (TSV) technology, which is used for Interconnect stacked chips, thereby enhancing performance, reducing signal transit time, and addressing issues such as signal latency.The research of antenna array microsystem is usually based on three-dimensional heterogeneous hybrid integration technology, typically multi-chip module (MCM) and system-in-package (SiP) technology. L), deposited thin film type (MCM-D) and co-fired ceramic type (MCM-C) interconnect substrate technologies.The research on high-density heterogeneous multi-layer substrates is a combination of substrate preparation technology, film integration technology, multi-layer substrate collaborative design and multi-physics coupling analysis, and reasonable process methods for matching and compatibility. High-density passive integrated heterogeneous multi-layer substrate or integrated passive device (IPD). Thick film passive component integrated substrate technology adopts advanced microelectronic technology and materials, built-in resistors, capacitors, Components such as inductors, as shown in Figure 10, can shorten the interconnection length of discrete devices, reduce parasitic effects, and reduce interconnection solder joints.Coolers based on micro-nano technology have played an increasingly important role in the thermal management of conventional micro-systems. At present, the heat dissipation of electronic systems has developed from traditional natural convection, metal heat conduction and forced air cooling to liquid cooling and heat pipe heat dissipation. The micro-channel heat dissipation in the cooling method is an effective and convenient cooling method for the antenna array microsystem. For example, the embedded micro-channel liquid-cooled substrate fabricated by LTCC technology has the advantages of small volume, large heat dissipation area, low power consumption, and high-volume Features such as low production cost. The channel cooler absorbs the heat on the chip, and transfers the heat to the outside through the liquid circulation to achieve the purpose of heat dissipation. Fractal flow channel. A schematic diagram of a typical 3D micro flow channel structure is shown in Figure 11. Taking advantage of the advantages that a single LTCC green ceramic sheet can be processed separately, a two-dimensional micro flow channel was fabricated on a single LTCC green ceramic sheet by a punching process , Laminate, hot-press, and sinter all green ceramic sheets to form a complete 3D microfluidic channel.Ceramic metal integrated packaging technology (integral substrate package, ISP) is to use the multi-layer substrate as the carrier of the package, which is connected to the cavity wall of the package shell. It is a hermetic package, no need to use an all-metal case. According to the boundary conditions such as environment, structure, size, etc., the temperature field distribution and the influence of different conditions on the temperature field, thermal resistance and heat dissipation path, mechanical load and structure are carried out. Analysis and optimization of microstructures such as stress and electromagnetic fields. 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